Method for accessing flash memory module and associated flash memory controller and memory device

ABSTRACT

A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of and claims the benefit of priorityto U.S. patent application Ser. No. 15/495,997, filed on Apr. 25, 2017,which claims priority of U.S. provisional application Ser. No.62/328,025 filed on Apr. 27, 2016 and priority of U.S. provisionalapplication Ser. No. 62/328,027 filed on Apr. 27, 2016, which areentirely incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a flash memory, and more particularlyto a method for accessing a flash memory module, a corresponding flashmemory controller, and a memory device.

2. Description of the Prior Art

In order to make a flash memory with higher storage density and morecapacity, the 3D flash memory manufacture becomes more important, and avariety of 3D NAND-type flash memory manufactures have been developed.For a conventional 3D NAND-type flash memory, since the manufacturestructure becomes totally different and positions of floating gates arechanged, it becomes more complicated for data writing and readingcompared to a traditional 2D NAND-type flash memory, and thus someserious problems arise. For example, for a certain 3D NAND-type flashmemories, multiple word lines may be defined as one word line set, andsuch word lines within the same word line set share the same controlcircuit. This inevitably causes that data errors also occur at floatinggate transistors on the other word lines within a word line set ifprogram fail occurs at floating gate transistors on one word line of thesame word line set. In addition, data errors also occur at floating gatetransistors on the other word lines within a word line set if one wordline is open or two word lines are short for the same word line set.Accordingly, it is important to provide an effective error correctionmechanism to maintain data integrity and accuracy as well as achievingthe advantage of lower circuit costs.

SUMMARY OF THE INVENTION

It is therefore one of the objectives of the present invention toprovide a method for accessing a flash memory module, a correspondingflash memory controller, and a memory device. The method employsRAID-like (Redundant Array of Independent Disks-like) error correctionmechanism without occupying more flash memory space and merely with lessbuffer memory space, to solve the problems mentioned above.

According to one embodiment of the present invention, a method foraccessing a flash memory module is disclosed, wherein the flash memorymodule is a 3D NAND-type flash memory module including a plurality offlash memory chips, each flash memory chip includes a plurality ofblocks which include a plurality of multiple-level cell blocks and aplurality of single-level cell (SLC) blocks, each block includes aplurality of data pages and includes a plurality of word linesrespectively disposed on a plurality of different planes and a pluralityof floating transistors controlled by a plurality of bit lines, thefloating transistors on each bit line forms at least one page among theplurality of data pages. The method comprises: encoding data to generateat least one parity check code, wherein the data is to be written into afirst super block of the flash memory chips, and the first super blockincludes one multiple-level cell block of each flash memory chip amongthe flash memory chips; writing the data into the first super block; andwriting the at least one parity check code into a second super block,wherein the second super block includes one SLC block of each flashmemory chip among the flash memory chips.

According to another embodiment of the present invention, a flash memorycontroller is disclosed, wherein the flash memory controller is used toaccess a flash memory module, the flash memory module is a 3D NAND-typeflash memory module including a plurality of flash memory chips, eachflash memory chip includes a plurality of blocks which include aplurality of multiple-level cell blocks and a plurality of single-levelcell (SLC) blocks, each block includes a plurality of data pages andincludes a plurality of word lines respectively disposed on a pluralityof different planes and a plurality of floating transistors controlledby a plurality of bit lines, the floating transistors on each bit lineforms at least one page among the plurality of data pages. The flashmemory controller comprises a memory, a microprocessor and a codec,where the memory is arranged for storing a program code, and themicroprocessor is arranged for executing the program code to controlaccess of the flash memory module. The codec encodes data to generate atleast one parity check code, wherein the data is to be written into afirst super block of the flash memory chips, and the first super blockincludes one multiple-level cell block of each flash memory chip amongthe flash memory chips; and the microprocessor writes the data into thefirst super block, and writes the at least one parity check code into asecond super block, wherein the second super block includes one SLCblock of each flash memory chip among the flash memory chips.

According to another embodiment of the present invention, a memorydevice is comprises a flash memory module and a flash memory controller.The flash memory module is a 3D NAND-type flash memory module includinga plurality of flash memory chips, each flash memory chip includes aplurality of blocks which include a plurality of multiple-level cellblocks and a plurality of single-level cell (SLC) blocks, each blockincludes a plurality of data pages and includes a plurality of wordlines respectively disposed on a plurality of different planes and aplurality of floating transistors controlled by a plurality of bitlines, the floating transistors on each bit line forms at least one pageamong the plurality of data pages. The flash memory controller isarranged for accessing the flash memory module, wherein when receiving awrite request from a host device to write data into the flash memorymodule, the flash memory controller encodes the data to generate atleast one parity check code, wherein the data is to be written into afirst super block of the flash memory chips, and the first super blockincludes one multiple-level cell block of each flash memory chip amongthe flash memory chips; and the flash memory controller writes the datainto the first super block, and writes the at least one parity checkcode into a second super block, wherein the second super block includesone SLC block of each flash memory chip among the flash memory chips.

According to another embodiment of the present invention, a method foraccessing a flash memory module is disclosed, wherein the flash memorymodule is a 3D NAND-type flash memory module including a plurality offlash memory chips, each flash memory chip includes a plurality ofblocks, each block includes a plurality of data pages and includes aplurality of word lines respectively disposed on a plurality ofdifferent planes and a plurality of floating transistors controlled by aplurality of bit lines, the floating transistors on each bit line formsat least one page among the plurality of data pages. The methodcomprises: configuring the flash memory chips to set at least one firstsuper block and at least one second super block of the flash memorychips; and allocating the at least one second super block to storetemporary parity check codes generated by an encoding procedure duringprogramming data into the at least one first super block.

According to another embodiment of the present invention, a flash memorycontroller is disclosed, wherein the flash memory controller is used toaccess a flash memory module, the flash memory module is a 3D NAND-typeflash memory module including a plurality of flash memory chips, eachflash memory chip includes a plurality of blocks, each block includes aplurality of data pages and includes a plurality of word linesrespectively disposed on a plurality of different planes and a pluralityof floating transistors controlled by a plurality of bit lines, thefloating transistors on each bit line forms at least one page among theplurality of data pages. The flash memory controller comprises a memory,a microprocessor and a codec, where the memory is arranged for storing aprogram code, and the microprocessor is arranged for executing theprogram code to control access of the flash memory module. In theoperations of the flash memory controller, the microprocessor configuresthe flash memory chips to set at least one first super block and atleast one second super block of the flash memory chips, and allocatesthe at least one second super block to store temporary parity checkcodes generated by an encoding procedure during programming data intothe at least one first super block.

According to another embodiment of the present invention, a memorydevice is comprises a flash memory module and a flash memory controller.The flash memory module is a 3D NAND-type flash memory module includinga plurality of flash memory chips, each flash memory chip includes aplurality of blocks, each block includes a plurality of data pages andincludes a plurality of word lines respectively disposed on a pluralityof different planes and a plurality of floating transistors controlledby a plurality of bit lines, the floating transistors on each bit lineforms at least one page among the plurality of data pages. The flashmemory controller is arranged for accessing the flash memory module,wherein the flash memory controller further configures the flash memorychips to set at least one first super block and at least one secondsuper block of the flash memory chips, and allocates the at least onesecond super block to store temporary parity check codes generated by anencoding procedure during programming data into the at least one firstsuper block.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a memory device according to an embodiment of thepresent invention.

FIG. 2 is a diagram of a 3D NAND-type flash memory.

FIG. 3 is a schematic diagram illustrating floating gate transistors.

FIG. 4 is a diagram illustrating multiple word line sets in one block.

FIG. 5 is a diagram illustrating an example of the flash memorycontroller programming data into the flash memory module.

FIG. 6 is a diagram illustrating an example of flash memory controllerprogramming data into the super block according to a first embodiment ofthe present invention.

FIG. 7 is a diagram showing an example of generating eight sets of finalparity check codes SF0-SF7 according to the parity check codes S0-S191shown in FIG. 6.

FIG. 8 is a flowchart of a method for accessing a flash memory moduleaccording to one embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 1, which is a diagram of a memory device 100according to an embodiment of the present invention. In the embodiment,the memory device 100 can be a portable memory device such as a memorycard conforming to the standards of SD/NMC, CF, MS, and XD. The memorydevice 100 comprises a flash memory module 120 and a flash memorycontroller 110. The flash memory controller 110 is used for accessingthe flash memory module 120. In the embodiment, the flash memorycontroller 110 comprises a microprocessor 112, read-only memory (ROM)112M, control logic 114, buffer memory 116, and an interface logic 118.The read-only memory is used for storing program codes 112C. Themicroprocessor 112 is used for executing the program codes 112C tocontrol the access of flash memory module 120. In other embodiments, thebuffer memory 116 can be configured outside of the controller 110, andis implemented with a storage space allocated by a dynamic random accessmemory.

Typically, the flash memory module 120 may include multiple flash memorychips each including a plurality of blocks. For example, the controller,e.g. flash memory controller 110 executing the program codes 112C byusing microprocessor 112, is arranged to perform copy, erase, and mergeoperations upon the flash memory module 120 wherein the copy, erase, andmerge operations are performed block by block. Additionally, a block canrecord a particular number of data pages wherein the controller, e.g.flash memory controller 110 executing the program codes 112C by usingmicroprocessor 112, is arranged to perform data programming upon theflash memory module 120 page by page.

In practice, the flash memory controller 110 executing the program codes112C by using the microprocessor 112 can perform a variety of controloperations by using its internal circuit elements. For instance, thecontroller 110 can use the control logic 114 to control the access offlash memory module 120 (more particularly to control the access of atleast one block or at least one data page), use the buffer memory 116 tobuffer data, and use the interface logic 118 to communicate with a hostdevice (not shown in FIG. 1).

Additionally, in the embodiment, the control logic 114 comprises a firstcodec 132 and a second codec 134. The first codec 132 is used forencoding data which is to be programmed/written into a block of flashmemory module 120 to generate a corresponding error correction codewherein the first codec 132 can generate the corresponding errorcorrection code by referring to content of a sector of a data page. Thegenerated error correction code with the content of the sector of thedata page is written/programmed into the data page. Additionally, thesecond codec 134 is a RAID (Redundant Array of Independent Disks)compressor/decompressor used for encoding data to be programmed intomultiple flash memory chips to generate corresponding parity checkcodes; the description is detailed later.

In the embodiment, the flash memory module 120 is a 3D NAND-type flashmemory module. Please refer to FIG. 2, which is a diagram of a 3DNAND-type flash memory. As shown in FIG. 2, the 3D NAND-type flashmemory comprises multiple floating gate transistors 202, and thestructure of 3D NAND-type flash memory is made up of multiple bit lines(e.g. BL1-BL3) and multiple word lines (e.g. WL0-WL2 and WL4-WL6). Onebit line can be also called one string. In FIG. 2, taking an example ofa top plane, at least one data page constitutes all floating gatetransistors on the word line WL0, and another at least one data pageconstitutes all floating gate transistors on the word line WL1; anotherat least one data page constitutes all floating gate transistors on theword line WL2, and other so on. Further, for example, the definition ofone data page (logic data page) and the relation between such data pageand word line WL0 may be different, and which may depend on differentdata programming types adopted by the flash memory. Specifically, allfloating gate transistors on the word line WL0 correspond to one singlelogic data page when the flash memory adopts single-level cell (SLC)data programming. All floating gate transistors on the word line WL0 maycorrespond to two, three, or four logic data pages when the flash memoryadopts multi-level cell (MLC) data programming. For example, atriple-level cell (TLC) memory structure means that all floating gatetransistors on the word line WL0 correspond to three logical data pages.Instead, a quad-level cell (QLC) memory structure means that allfloating gate transistors on the word line WL0 correspond to fourlogical data pages. The description for the TLC memory structure or QLCmemory structure is not detailed here for brevity. Additionally, for theprogram/erase operation of flash memory controller 110, one data page isa minimum data unit which is programmed by the controller 110 into themodule 120, and one block is a minimum data unit which is erased by thecontroller 110; that is, the controller 110 programs at least one datapage for one data programming operation, and erases at least one blockfor one erase operation.

Please refer to FIG. 3, which is a schematic diagram illustratingfloating gate transistors 202. As shown in FIG. 3, the gate and floatinggate of each floating gate transistor are disposed all around its sourceand drain, to improve the capability of channel sensing.

It should be noted that the examples of 3D NAND-type flash memory andfloating gate transistors 202 shown in FIG. 2 and FIG. 3 are not meantto be limitations of the present invention. In other embodiments, 3DNAND-type flash memory may be designed or configured as differentstructures; for example, a portion of word lines may be mutuallyconnected. Also, the design or configuration of floating gate transistor202 may be modified as different structures.

As mentioned above, in some conventional 3D NAND-type flash memorystructure, multiple word lines are defined as or classified into a wordline set, i.e. a set of word lines, and such word line set correspond toor include a common control circuit. This inevitably causes that dataerrors occur at other floating gate transistors on the other word linesof such word line set when programming data to the floating gatetransistors on a word line of such word line set fails. In theembodiment, the word lines disposed/positioned on the same plane isconfigured as or classified into a word line set. Refer back to FIG. 2.Word lines WL0-WL3 are classified into a first word line set, and wordlines WL4-WL7 are classified into a second word line set; and other soon. Refer to FIG. 4, which is a diagram illustrating multiple word linesets in one block. As shown in FIG. 4, it is assumed that the block hasforty-eight 3D stacked planes, i.e. 48 word line sets. Each word lineset has four word lines and thus has all transistors on total onehundred and ninety-two word lines. As shown in FIG. 4, the block hasforty-eight word line sets which are represented by WL_G0-WL_G47.Additionally, in this figure, the block is a TLC block. That is,floating gate transistors on each word line can be used for storing datacontent of three data pages. As shown by FIG. 4, for example, floatinggate transistors on word line WL0 included by the word line set WL_G0can be used for storing lower data page P0L, middle data page P0M, andupper data page P0U. The floating gate transistors on word line WL1included by the word line set WL_G0 can be used for storing lower datapage P1L, middle data page P1M, and upper data page P1U. The floatinggate transistors on word line WL2 included by the word line set WL_G0can be used for storing lower data page P2L, middle data page P2M, andupper data page P2U. The floating gate transistors on word line WL3included by the word line set WL_G0 can be used for storing lower datapage P3L, middle data page P3M, and upper data page P3U. When thecontroller 110 programs or writes data into the data pages of word lineset WL_G0, the controller 110 is arranged for sequentially programs datainto the floating gate transistors on word lines WL0, WL1, WL2, and WL3.Even if data is successfully programmed into word lines WL0 and WL1 butprogramming other data into word line WL2 fails (i.e. program fail),programming fail will occur at the word line set WL_G0 since the programfail of word line WL2 causes errors at the word lines WL0 and WL1.

Further, in some situations, even data has been successfully programmedinto the word line set WL_G0, there is a possibility that the datacannot be readout from word line set WL_G0 or reading errors occur. Forinstance, the data cannot be read if one word line open occurs; all thedata of one word line set will become erroneous if one word line in suchword line set is open. Further, if two word lines in different word linesets are shorted (e.g. word lines WL3 and WL4 are shorted), then all thedata of two word line sets WL_G0 and WL_G1 cannot be read successfully.That is, the two word line sets WL_G0 and WL_G1 are equivalentlyshorted.

As mentioned above, since data errors may occur at one or two adjacentword line set(s) due to the program fail, word line open, and word lineshort when programming data into or reading data from a flash memory, tosolve the problems, in the embodiment a method/mechanism for accessingflash memory module 120 is provided. One of the advantages is that themethod/mechanism merely consumes less resource (i.e. occupies lessmemory space). The description of the method/mechanism is detailed inthe following.

FIG. 5 is a diagram illustrating an example of the flash memorycontroller 110 programming data into the flash memory module 120. Asshown in FIG. 5, the flash memory module 120 comprises multiple channels(in the embodiment, two channels 510 and 520), and each channelcorresponds to a sequencer of flash memory controller 110 and comprisesmultiple flash memory chips. In the embodiment, the channel 510comprises flash memory chips 512 and 514, and the channel 520 comprisesflash memory chips 522 and 524. Additionally, a super block consists ofone block of each flash memory chip 512, 514, 522, and 524. The flashmemory controller 110 is arranged for programming data by super blocks.In the embodiment, the super block 530 comprises one TLC block of eachflash memory chip 512, 514, 522, and 524; and the super block 540comprises one SLC block of each flash memory chip 512, 514, 522, and524. In other embodiments, the super block 530 may comprise one QLCblock of each flash memory chip 512, 514, 522, and 524. This is notmeant to be a limitation.

Refer to FIG. 5 and FIG. 6 together, where FIG. 6 is a diagramillustrating an example of flash memory controller 110 programming datainto the super block 530 according to a first embodiment of the presentinvention. Each data unit is programmed into respective one page of theflash memory chips 512, 514, 522, and 524. For instance, the first dataunit is programmed into the data pages P0 of flash memory chips 512,514, 522, and 524. The second data unit is programmed into the datapages P1 of the flash memory chips 512, 514, 522, and 524; and others soon. The (N)-th data unit is programmed into the data pagse P(N−1) of theflash memory chips 512, 514, 522, and 524; for example, N is equal to192. Refer to FIG. 6, when the flash memory controller 110 is arrangedto program the first data unit into the super block 530, the first codec132 encodes different portions of the first data unit to generatecorresponding error correction codes, and then the first data unit withthe corresponding error correction codes generated by the first codec132 are to be programmed into a first data page P0 of each of flashmemory chips 512, 514, 522, and 524. Specifically, the first codec 132encodes a first data portion of the first data unit to generate an errorcorrection code, and the first data portion with the generated errorcorrection code are to be programmed into first data page P0 of flashmemory chip 512. The first codec 132 then encodes a second data portionof the first data unit to generate an error correction code, and thesecond data portion with the generated error correction code are to beprogrammed into the first data page P0 of flash memory chip 514. Thefirst codec 132 then encodes a third data portion of the first data unitto generate an error correction code, and the third data portion withthe generated error correction code are to be programmed into the firstdata page P0 of flash memory chip 522. The first codec 132 then encodesa fourth data portion (a last data portion) of the first data unit togenerate an error correction code, and the fourth data portion with thegenerated error correction code are to be programmed into the first datapage P0 of flash memory chip 524. It should be noted that the operationof first codec 132 can be performed upon one sector data each time, andeach data page consists of multiple sectors. Before programming/writingthe first data unit with the error correction codes generated by thefirst codec 132 into the super block 530, the second codec 134 of flashmemory controller 110 is arranged for performing RAID encoding upon thefirst data unit with the error correction codes to generate a firstparity check code S0. In one embodiment, the second codec 134 can employRS (Reed-Solomon) encoding operation or XOR (exclusive-OR) encodingoperation upon the data content to be programmed into the first datapage P0 of each of flash memory chips 512, 514, 522 and 524, to generatethe first parity check code S0. For example, the second codec 134 can bearranged to perform an XOR encoding operation upon first bits of thefirst data pages P0 of the flash memory chips 512, 514, 522 and 524 togenerate a first bit of the first parity check code S0, the second codec134 can be arranged to perform an XOR encoding operation upon secondbits of the first data pages P0 of the flash memory chips 512, 514, 522and 524 to generate a second bit of the first parity check code S0, thesecond codec 134 can be arranged to perform an XOR encoding operationupon third bits of the first data pages P0 of the flash memory chips512, 514, 522 and 524 to generate a third bit of the first parity checkcode S0, and so on.

The first parity check code S0 generated by second codec 134 is used forcorrecting error(s) occurring at the first data page P0 of anyone flashmemory chip among the flash memory chips 512, 514, 522, and 524. Forexample, if errors occur at the first data page P0 of flash memory chip512 and cannot be corrected by the error correction codes generated byfirst codec 132, the second codec 134 can be arranged to read datacontent of all first data pages P0 of other flash memory chips 514, 522,524 and the first parity check code S0 to perform error correction so asto determine correct data content of the first data page P0 of the flashmemory chip 512.

Further, the first parity check code S0 generated by second codec 134can be temporarily stored in the buffer memory 116 of the flash memorycontroller 110.

Further, during data programming of the first data unit, the flashmemory controller 110 can be arranged to read and then check the data todetermine whether the data has been programmed successfully. When thedata is erroneously programmed or program fails, the second codec 134can directly use the first parity check code S0 stored in the buffermemory 116 to correct the data which has been read for checking. Sincethe flash memory module 120 does not directly correct/modify data whichhas been programmed, the corrected data (i.e. the first data unit hasbeen corrected) with other data of super block 530 can be programmedinto another super block after a waiting time period. In addition, afterthe flash memory controller 110 determines that the first data unit isprogrammed/written into the first page P0 of the flash memory chips 512,514, 522 and 524 successfully, the flash memory controller 110 will movethe first parity check code S0 from the buffer memory 116 to the superblock 540.

When the flash memory controller 110 is arranged to program a seconddata unit into the super block 530, the first codec 132 encodesdifferent portions of the first data unit to generate correspondingerror correction codes, and then the second data unit with thecorresponding error correction codes generated by the first codec 132are to be programmed into a second data page P1 of each of flash memorychips 512, 514, 522, and 524. Before programming/writing the second dataunit with the error correction codes generated by the first codec 132into the super block 530, the second codec 134 of flash memorycontroller 110 is arranged for performing RAID encoding upon the seconddata unit with the error correction codes to generate a second paritycheck code S1. In one embodiment, the second codec 134 can employ RS(Reed-Solomon) encoding operation or XOR (exclusive-OR) encodingoperation upon the data content to be programmed into the second datapage P1 of each of flash memory chips 512, 514, 522 and 524, to generatethe second parity check code S1.

Further, the second parity check code S1 generated by second codec 134can be temporarily stored in the buffer memory 116 of flash memorycontroller 110.

Similarly, during data programming of the second data unit, the flashmemory controller 110 can be arranged to read and then check the data todetermine whether the data has been programmed successfully. When thedata is erroneously programmed or program fails, the second codec 134can directly use the second parity check code S1 stored in the buffermemory 116 to correct the data which has been read for checking. Sincethe flash memory module 120 does not directly correct/modify data whichhas been programmed, the corrected data (i.e. the second data unit hasbeen corrected) with other data of super block 530 can be programmedinto another super block after a waiting time period.

It should be noted that the data pages P0 of flash memory chips 512,514, 522 and 524 may be damaged when data is erroneously programmedduring data programming of the second data unit since the data pages P0and P1 belong to the same word line set WL_G0. For instance, if data iserroneously programmed into the data page P1 of flash memory chip 514during data programming of the second data unit, then errors will occurat the data page P0 in flash memory chip 514, which has beensuccessfully programmed. In this situation, because the first paritycheck code S0 may be not stored in the buffer memory 116, the flashmemory controller 110 can read the first parity check code S0 from thesuper block 540 to correct the first data unit which is read out fromthe super block 530.

Based on the same operation, the flash memory controller 110programs/writes a third data unit into the third data pages P2 of flashmemory chips 512, 514, 522 and 524 and generates a corresponding thirdparity check code S2, and then programs/writes a fourth data unit intothe fourth data pages P3 of flash memory chips 512, 514, 522, and 524and generates a corresponding fourth parity check code S3. After that,data programming for the word line set WL_G0 is completed.

Similarly, the flash memory controller 110 then is arranged forrespectively programming/writing the fifth, sixth, seventh, . . . , and(184)-th data units into flash memory chips 512, 514, 522 and 524,wherein the second codec 134 is arranged for performing the encodingoperation upon the fifth, sixth, seventh, . . . , and (184)-th dataunits to respectively generate different parity check codes S4-S183.Then, the parity check codes S4-S183 are stored into the super block540.

For the last two word line sets WL_G46 and WL_G47 of super block 530,the controller 110 is arranged for processing corresponding parity checkcodes and programming the processed parity check codes into data pagesP184-P191 of the last chip (i.e. chip 524). In order to solve theproblems generated due to program fail, word line open, and word lineshort of word line set(s), the controller 110 is arranged to classifyall word line sets into a group of multiple odd word line sets (i.e.WL_G0, WL_G2, WL_G4, WL_G6, . . . , WL_G44, and WL_G46) and a group ofmultiple even multiple word line sets (i.e. WL_G1, WL_G3, WL_G5, WL_G7,. . . , WL_G45, and WL_G47) according to the order of data programmingwhen processing corresponding parity check codes. For the (185)-th dataunit, the flash memory controller 110 is arranged forprogramming/writing the (185)-th data unit with the error correctioncode generated by first codec 132 into the data pages P184 of flashmemory chips 512, 514, and 522 (i.e. the last word line set WL_G46 amongthe group of odd word line sets), and does not program the data into thedata page P184 of flash memory chip 524. Before programming/writing the(185)-th data unit into super block 530, the second codec 134 isarranged for encoding the (185)-th data unit and the corresponding errorcorrection code to generate the (185)-th parity check codes S184. Forexample, the flash memory controller 110 is arranged for reading thefirst parity check code (S0, S8, S16, . . . , S176) of each word lineset among the group of odd word line sets (i.e. WL_G0, WL_G2, WL_G4,WL_G6, . . . , WL_G44) from the super block 540, and the second codec134 is arranged for performing XOR operation upon the parity check codes(S0, S8, S16, . . . , S176) with parity check codes S184 to generate afinal parity check code SF0. The flash memory controller 110 thenprograms the (185)-th data unit into the data pages P184 of the flashmemory chips 512, 514 and 522, and programs the final parity check codeSF0 into the data page P184 of flash memory chip 524. In one embodiment,the second codec 134 performs XOR operation upon first bits of theparity check codes (S0, S8, S16, . . . , S184) to generate a first bitof the final parity check code SF0, and the second codec 134 performsXOR operation upon second bits of the parity check codes (S0, S8, S16, .. . , S184) to generate a second bit of the final parity check code SF0,and so on. In addition, the (185)-th parity check codes S184 can bestored into the super block 540.

For the (186)-th data unit, the flash memory controller 110 is arrangedfor programming/writing the (186)-th data unit with the error correctioncode generated by first codec 132 into the data pages P185 of flashmemory chips 512, 514 and 522 (i.e. the last word line set WL_G47 amongthe group of odd word line sets), and does not program the data into thedata page P185 of flash memory chip 524. Before programming/writing the(186)-th data unit into super block 530, the second codec 134 isarranged for encoding the (186)-th data unit and the corresponding errorcorrection code to generate the (186)-th parity check codes S185. Forexample, the flash memory controller 110 is arranged for reading theparity check codes (S1, S9, S17, . . . , S177) of each word line setamong the group of odd word line sets (i.e. WL_G0, WL_G2, WL_G4, WL_G6,. . . , WL_G44) from the super block 540, and the second codec 134 isarranged for performing XOR operation upon the parity check codes (S1,S9, S17, . . . , S177) with parity check codes S185 to generate a finalparity check code SF1. The flash memory controller 110 then programs the(186)-th data unit into the data pages P185 of the flash memory chips512, 514 and 522, and programs the final parity check code SF1 into thedata page P185 of flash memory chip 524. In one embodiment, the secondcodec 134 performs XOR operation upon first bits of the parity checkcodes (S1, S9, S17, . . . , S185) to generate a first bit of the finalparity check code SF1, and the second codec 134 performs XOR operationupon second bits of the parity check codes (S1, S9, S17, . . . , S185)to generate a second bit of the final parity check code SF1, and so on.In addition, the (186)-th parity check codes S185 can be stored into thesuper block 540.

Based on the similar operation, for the (187)-th-(192)-th data units,the flash memory controller 110 is arranged for programming/writing the(187)-th-(192)-th data units with corresponding error correction codesgenerated by first codec 132 into data pages P186-P191 of the flashmemory chips 512, 514 and 522. The second codec 134 also generates finalparity check codes SF2-SF7 based on similar operations, and the finalparity check codes SF2-SF7 are respectively programmed/written into datapages P186-P191 of the flash memory chip 524.

The operations for generating the final parity check codes SF0-SF7according to the multiple parity check codes S0-S191 are illustrated inFIG. 7.

In this embodiment, the parity check codes stored in the super block 540serve as temporary parity check codes, that is the parity check codesS0-S191 stored in the super block 540 are used only when the an error(the data is erroneously programmed or program fails) occurs during theprogramming operation of the data written into the super block 530.Therefore, after the final parity check codes SF0-SF7 are written intothe super block 530, the parity check codes S0-S191 stored in the superblock 540 are no longer needed. Hence, the flash memory controller 110can delete the contents of the super block 540 or mark the super block540 as invalid/ineffective even if the contents within the super blockare effective.

It should be noted that the above-mentioned final parity check codesSF0-SF7 are correspondingly generated based on the parity check codesS0-S191. The final parity check codes SF0-SF7 substantially carryinformation of each of the parity check codes S0-S191. That is, each ofmultiple parity check codes S0-S191 can be obtained according tocorresponding data pages of flash memory chips. For example, the paritycheck codes S1 can be obtained by reading data from the data pages P1 offlash memory chips 512, 514, 522 and 524. Thus, the final parity checkcodes SF0-SF7 can be used to correct errors if data errors occur. Forinstance, if one word line in the word line set WL_G0 is open (e.g. aword line corresponding to data pages P0 of flash memory chip 514 isopen), the flash memory controller 110 can re-generates the parity checkcodes S8, S16, . . . , S184 and final parity check code SF0 by readingdata from other word line sets so as to re-generate the parity checkcode S0, and then can use the parity check code S0 and data content readfrom the data pages P0 of flash memory chips 512, 522, and 524 togenerate data of the data page P0 of flash memory chip 514. The flashmemory controller 110 can re-generate the parity check codes S9, S17, .. . , S185 and final parity check code SF1 by reading data from otherword line sets so as to re-generate the s parity check code S1, and thencan use the parity check code S1 and data content read from the datapages P1 of flash memory chips 512, 522, and 524 to generate data of thedata page P1 of flash memory chip 514. Also, the flash memory controller110 can re-generate data of data pages P2 and P3 of flash memory chip514 similarly. As mentioned above, by the above operations, the dataerrors can be properly corrected to recover the data only if no multipleword lines in super block 530 are open simultaneously.

Additionally, if two word lines respectively positioned at word linesets WL_G0 and WL_G1 are short (e.g. two word lines correspondingly tothe data pages P3 and P4 of flash memory chip 514 are short), thecorresponding data can be also properly corrected to recover the datacontent of word line sets WL_G0 and WL_G1.

It should be noted that each of the data pages P0-P191 shown in FIG. 6in other embodiments may indicate to comprise two or four data pages andis not limited to comprise only three data pages. For example, in theMLC flash memory structure, each of the data pages P0-P191 has two datapages; in the QLC flash memory structure, each of the data pages P0-P191has four data pages.

In the embodiments shown in FIG. 6 and FIG. 7, the final parity checkcodes SF0-SF7 are generated by reading the parity check codes stored inthe super block 540, however, it is not a limitation of the presentinvention. In another embodiment, the parity check code to be stored inthe super block 540 can be encoded by using the parity check codecorresponding to the previous word line set. For example, the secondcodec 134 can encode the 9^(th) data unit with the first parity checkcode S0 to generate the ninth parity check code S8, the second codec 134can encode the 17^(th) data unit with the ninth parity check code S8 togenerate the 17^(th) parity check code S16, . . . , and the second codec134 can encode the 185^(th) data unit with the 177^(th) parity checkcode S176 to generate the 185^(th) parity check code S184. Therefore,because the 185^(th) parity check code S184 carry the information of theprevious parity check codes S0, S8, S16, . . . , and S176, the 185^(th)parity check code S184 can serve as the final parity check code SF0, andthe 185^(th) parity check code S184 can be directly stored into the datapage P184 of the flash memory chip 524. Similarly, the final paritycheck codes SF1-SF7 can be generated by using the aforementioned method,and the final parity check codes SF1-SF7 stored into the data pagesP185-P191 of the flash memory chip 524, respectively.

Additionally, in the embodiment of FIG. 5, the super block 530 consistsof one TLC block of each of flash memory chips 512, 514, 522, and 524.However, in other embodiments, the flash memory module 120 may beconfigured as two block planes, and the super block 530 consists of twoTLC blocks of each of flash memory chips 512, 514, 522, and 524. The twoblock planes within one chip is controlled by different chip enablesignals. Similarly, the super block 540 may consist of two SLC blocks ofeach of flash memory chips 512, 514, 522, and 524.

Refer to FIG. 8, which is a flowchart of a method for accessing a flashmemory module according to one embodiment of the present invention.Referring to the aforementioned disclosure, the flow is described asfollows.

Step 800: the flow starts.

Step 802: configure a plurality of flash memory chips to set at least afirst super block and at least a second super block of the flash memorychips.

Step 804: write data into the first super block.

Step 806: encode the data to generate a plurality of temporary paritycheck codes, the store the temporary parity check codes into the secondsuper block.

Step 808: generate a final parity check code according to the temporaryparity check codes.

Step 810: write the final parity check code into the first super block.

Step 812: erase the second super block or mark the second super block asinvalid or ineffective.

Step 814: the flow finishes.

To simply describe the spirits of the present invention, for the methodfor accessing the flash memory module, the second codec is arranged forsequentially performing encoding operations for multiple different dataof multiple-layer blocks in one super block and storing temporary paritycheck codes, which are correspondingly generated, in a SLC super block.The second codec then is arranged for reading the temporary parity checkcodes stored in the SLC super block to generate final parity check codeshaving less data amount, and for storing the final parity check codes inlast data pages of the odd word line sets and in last data pages of theeven word line sets. By doing so, in addition to being capable ofproperly correcting data errors generated due to program fail, word lineopen, and word line short, the needed storage space of buffer memory inthe flash memory controller can be significantly decreased, and it isnot required to employ too much storage space to store the parity checkcodes. That is, the circuit costs of flash memory controller can bereduced, and the efficiency for using the flash memory module isimproved greatly.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A method for accessing a flash memory module,wherein the flash memory module is a 3D NAND-type flash memory moduleincluding a plurality of flash memory chips, each flash memory chip is a3D flash memory chip, each flash memory chip includes a plurality ofblocks, each block includes a plurality of data pages, and the methodcomprises: configuring the flash memory chips to set at least one firstsuper block and at least one second super block of the flash memorychips; allocating the at least one second super block to store temporaryparity check codes generated by an encoding procedure during programmingdata into the at least one first super block; reading a plurality oftemporary parity check codes from the second super block; generating aplurality of final parity check codes according to the temporary paritycheck codes, wherein each final parity check code is generated by usingthe temporary parity check codes corresponding to the data stored indifferent word line groups of the first super block, and each word linegroup has a plurality of word lines; and writing the plurality of finalparity check codes into the first super block.
 2. The method of claim 1,wherein the second super block is dedicated to store the temporaryparity check codes generated by the encoding procedure duringprogramming data into the at least one first super block.
 3. The methodof claim 1, wherein the first super block includes one multiple-levelcell block of each flash memory chip among the flash memory chips, andthe second super block includes one single-level cell (SLC) block ofeach flash memory chip among the flash memory chips.
 4. The method ofclaim 3, wherein the multiple-level cell block is a triple-level cell(TLC) block or a quad-level cell (QLC) block.
 5. The method of claim 1,further comprising: during the data being written into the super block:reading a portion of the data, which has been written into the firstsuper block, from the first super block; and reading at least oneportion of the temporary parity check codes from the second super block,and using the at least one portion of the temporary parity check codesto perform error correction upon the portion of the data when an erroroccurs and cannot be corrected during reading the portion of the data.6. The method of claim 1, further comprising: after the final paritycheck code is written into the first super block, erasing contents ofthe second super block or marking the second super block asinvalid/ineffective even if the data stored in the first super block isvalid/effective.
 7. The method of claim 1, further comprising: after thefinal parity check code is written into the first super block: reading aportion of the data from the first super block; and when an error occursand cannot be corrected during reading the portion of the data, readingthe final parity check code from the first super block, and using thefinal parity check code to perform error correction upon the portion ofthe data.
 8. A flash memory controller, wherein the flash memorycontroller is used to access a flash memory module, the flash memorymodule is a 3D NAND-type flash memory module including a plurality offlash memory chips, each flash memory chip is a 3D flash memory chip,each flash memory chip includes a plurality of blocks, each blockincludes a plurality of data pages, and the flash memory controllercomprises: a memory, for storing a program code; a microprocessor, forexecuting the program code to control access of the flash memory module;and a codec; wherein the microprocessor configures the flash memorychips to set at least one first super block and at least one secondsuper block of the flash memory chips, and allocates the at least onesecond super block to store temporary parity check codes generated by anencoding procedure during programming data into the at least one firstsuper block; wherein the microprocessor reads a plurality of temporaryparity check codes from the second super block, the codec generates aplurality of final parity check codes according to the temporary paritycheck codes, and the microprocessor writes the plurality of final paritycheck codes into the first super block, wherein each final parity checkcode is generated by using the temporary parity check codescorresponding to the data stored in different word line groups of thefirst super block, and each word line group has a plurality of wordlines.
 9. The flash memory controller of claim 8, wherein the secondsuper block is dedicated to store the temporary parity check codesgenerated by the encoding procedure during programming data into the atleast one first super block.
 10. The flash memory controller of claim 8,wherein the first super block includes one multiple-level cell block ofeach flash memory chip among the flash memory chips, and the secondsuper block includes one single-level cell (SLC) block of each flashmemory chip among the flash memory chips.
 11. The flash memorycontroller of claim 10, wherein the multiple-level cell block is atriple-level cell (TLC) block or a quad-level cell (QLC) block.
 12. Theflash memory controller of claim 8, wherein during the data is writteninto the super block: the microprocessor reads a portion of the data,which has been written into the first super block, from the first superblock; and the microprocessor reads at least one portion of thetemporary parity check codes from the second super block, and the codecuses the at least one portion of the temporary parity check codes toperform error correction upon the portion of the data when an erroroccurs and cannot be corrected during reading the portion of the data.13. The flash memory controller of claim 8, wherein after the finalparity check code is written into the first super block, themicroprocessor erases contents of the second super block or marks thesecond super block as invalid/ineffective even if the data stored in thefirst super block is valid/effective.
 14. The flash memory controller ofclaim 8, wherein after the final parity check code is written into thefirst super block: the microprocessor reads a portion of the data fromthe first super block; and when an error occurs and cannot be correctedduring reading the portion of the data, the microprocessor reads thefinal parity check code from the first super block, and the codec usesthe final parity check code to perform error correction upon the portionof the data.
 15. A memory device, comprising: a flash memory module,wherein the flash memory module is a 3D NAND-type flash memory moduleincluding a plurality of flash memory chips, each flash memory chip is a3D flash memory chip, each flash memory chip includes a plurality ofblocks, each block includes a plurality of data pages; and a flashmemory controller, for accessing the flash memory module; wherein theflash memory controller configures the flash memory chips to set atleast one first super block and at least one second super block of theflash memory chips, and allocates the at least one second super block tostore temporary parity check codes generated by an encoding procedureduring programming data into the at least one first super block; whereinthe flash memory controller reads a plurality of temporary parity checkcodes from the second super block, generates a plurality of final paritycheck codes according to the temporary parity check codes, and writesthe plurality of final parity check codes into the first super block,wherein each final parity check code is generated by using the temporaryparity check codes corresponding to the data stored in different wordline groups of the first super block, and each word line group has aplurality of word lines.
 16. The memory device of claim 15, wherein thesecond super block is dedicated to store the temporary parity checkcodes generated by the encoding procedure during programming data intothe at least one first super block.
 17. The memory device of claim 15,wherein the first super block includes one multiple-level cell block ofeach flash memory chip among the flash memory chips, and the secondsuper block includes one single-level cell (SLC) block of each flashmemory chip among the flash memory chips.
 18. The memory device of claim17, wherein the multiple-level cell block is a triple-level cell (TLC)block or a quad-level cell (QLC) block.
 19. The memory device of claim15, wherein during the data is written into the super block: the flashmemory controller reads a portion of the data, which has been writteninto the first super block, from the first super block; and the flashmemory controller reads at least one portion of the temporary paritycheck codes from the second super block, and uses the at least oneportion of the temporary parity check codes to perform error correctionupon the portion of the data when an error occurs and cannot becorrected during reading the portion of the data.